Fractal Semiconductor

The Opportunity

01 / 03

Yield ramp is the bottleneck

New process nodes crawl through years of trial-and-error before reaching stable high-volume yields, delaying innovations and bleeding revenue at scale.

02 / 03

Silent yield loss is expensive

Drift that stays within spec still slips through as yield loss — while root-cause hunts pull tools offline for days.

03 / 03

Geopolitical moment demands urgency

Federal capital is flooding into domestic fabs to develop frontier chips like RF and quantum. The window to lead is now.

5–15yr

Typical lab-to-fab transfer time for a new process innovation

400-600

Of suspect process steps

$52B+

Committed under the CHIPS and Science Act

Areas of Research

Tackling the biggest issues
in frontier chip manufacturing

Mission I

Process Discovery for Accelerated Yield Ramp

Physics-informed ML models to simulate equipment-level behavior to aid discovery of optimal process recipes in silico, collapsing the trial-and-error cycle that stretches new-node ramps into years.

Mission II

Intelligent First-Principles Yield Protection

First-principles models to trace yield excursions back to their physical source: surfacing the in-spec drift that conventional APC/SPC misses, so engineers find root cause without pulling tools offline.

Vision/Roadmap

01 / 03 — Bridging the lab-to-fab gap

Compressing the distance between discovery and production

A new process recipe discovered in the research lab today takes years to translate into stable high-volume manufacturing. We're building the software infrastructure to collapse that timeline — so breakthroughs reach the production line faster, at higher yield, with less waste.

02 / 03 — Intelligent, autonomous fabs

From passive monitoring to active, closed-loop control

The fab of the future doesn't wait for an engineer to notice drift. It detects anomalies in real time, recalibrates tools automatically, and continuously tightens its own process window — moving beyond dashboards toward genuine autonomous control.

03 / 03 — New fab models

Prototyping fabs, fab-in-a-box, and the software-defined supply chain

When process intelligence is fully software-defined, smaller and more agile fab configurations become viable — enabling rapid hardware iteration, distributed sovereign manufacturing, and purpose-built prototyping environments that evolve in weeks, not years.

Get in Touch

Request a Research Briefing

Our roadmap begins with a physics-informed ML model of Atomic Layer Deposition (ALD): a process at the frontier of the PIML literature, and where the gap between simulation and fab-floor reality is both acute and uniquely addressable.

From there we expand across the process stack, toward a full digital twin of the fab floor, and ultimately closed-loop autonomous control. We're talking with foundries, researchers, and engineers working at this boundary. If that's you, we'd like to hear from you.

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Interested in research partnerships or early-stage engineering internships? We review researcher profiles on a rolling basis.

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Digital Twins for Semiconductor Fabs